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SX1211
WIRELESS & SENSING
Read Byte (after/during Rx)
To read bytes from the FIFO the timing diagram below should be carefully followed by the uC.
1
2
3
4
5
6
7
8
1
2
3
4
5
6
7
8
NSS_DATA (In)
SCK (In)
MOSI (In)
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
1 st byte read
2
nd
byte read
MISO (Out) HZ
(input)
D1(7)
D1(6) D1(5)
D1(4) D1(3)
D1(2) D1(1) D1(0)
HZ
(input)
D2(7) D2(6)
D2(5)
D2(4)
D2(3)
D2(2)
D2(1)
D2(0)
HZ
(input)
Figure 30: Read Bytes Sequence (ex: 2 bytes)
Note that it is compulsory to toggle NSS_DATA back high between each byte read.
5.2.2. FIFO
5.2.2.1. Overview and Shift Register (SR)
In Buffered and Packet modes of operation, both data to be transmitted and that has been received are stored in a
configurable FIFO (First In First Out) device. It is accessed via the SPI Data interface and provides several
interrupts for transfer management.
The FIFO is 1 byte (8 bits) wide hence it only performs byte (parallel) operations, whereas the demodulator
functions serially. A shift register is therefore employed to interface the two devices. In transmit mode it takes bytes
from the FIFO and outputs them serially (MSB first) at the programmed bit rate to the modulator. Similarly, in Rx the
shift register gets bit by bit data from the demodulator and writes them byte by byte to the FIFO. This is illustrated in
figure below.
byte1
byte0
FIFO
Data Tx/Rx
8
SR (8bits)
1
MSB
LSB
Figure 31: FIFO and Shift Register (SR)
5.2.2.2. Size Selection
The FIFO width is programmable, to 16, 32, 48 or 64 bytes via MCParam_Fifo_size
Rev 8 – February 2013
Page 38 of 92
www.semtech.com
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